A transient blocking unit (TBU) is an arrangement of two or more transistors connected such that they rapidly and automatically switch off in response to an over-voltage or over-current situation. This functionality allows TBUs to provide protection for series-connected loads. Typical TBU designs rely on the threshold voltage of a depletion mode (i.e., normally on) transistor in order to set the TBU trip current. Unfortunately, the threshold voltage of a depletion mode transistor tends to be a relatively poorly controlled device parameter in fabrication.
A TBU can be a bi-directional TBU or a unidirectional TBU. The bi-directional TBU 100, as shown in FIG. 1, includes a pair of first-material depletion mode devices 102 each having a drain terminal 104 connected to a separate the sense terminal 106, and a second-material depletion mode device 108 having a conductive channel 110 connected between and in series with the pair of first-material depletion mode devices 102, where a gate terminal 112 of the second-material depletion mode device 108 is electrically connected to the drain terminal 114 of each the first-material depletion mode devices 102. According to one aspect of the bi-directional TBU 100, the gate terminal 112 of the second-material depletion mode device 108 is resistively connected 116 to the drain terminal 104 of each the first-material depletion mode devices 102. In another aspect of the bi-directional TBU 100, a diode 118 is connected between the gate terminal 112 of the second-material depletion mode device 108 and the drain terminal 104 of each the first-material depletion mode devices 102, where a cathode of the diode 118 is connected to the gate terminal 112 of the second-material depletion mode device 108 and an anode of the diode 118 is connected to the drain terminal 104 of the first-material depletion mode device 102. Further, drive of the gate 120 of the first-material depletion mode device 102 is triggered by detection of a current through the TBU 100 by virtue of the voltage developed across channel 110 of second-material depletion mode device 108. In another aspect of the bi-directional TBU 100, the first-material depletion mode device 102 is a p-type depletion mode device and the second-material depletion device 108 is an n-type depletion mode device. In a further aspect of bi-directional TBU 100, the first-material depletion mode device 102 is an n-type depletion mode device and the second-material depletion device 108 is a p-type depletion mode device.
The unidirectional TBU 200 as shown in FIG. 2, includes a first-material depletion mode device 102 having a drain terminal 104 connected to a first the sense terminal 106, a second-material depletion mode device 108 having a conductive channel 110 connected in series with a source 114 of the first-material depletion mode device 102 and a second sense terminal 106, where a gate 112 of the second-material depletion mode device 108 is resistively connected 116 to a drain 104 of the first-material depletion mode device 102. Further, a gate 120 of the first-material depletion mode device 102 is triggered by detection of a current through the TBU 200. In another aspect of the unidirectional TBU 200, the first-material depletion mode device 102 is a p-type depletion mode device and the second-material depletion device 108 is an n-type depletion mode device. In a further aspect of the unidirectional TBU 200, the first-material depletion mode device 102 is an n-type depletion mode device and the second-material depletion device 108 is a p-type depletion mode device.
The TBU presents a problem in mass production: the basic design is sensitive to tolerance in the depletion mode NMOS, for example. The bi-directional TBU shown in FIG. 1 is used as a reference for a conventional TBU approach for comparison, but the basic design considerations are applicable to all TBU types, independent of the implementation of gate feedback to the PJFET, for example. Also the same concepts can be applied to a unidirectional TBU 200 of FIG. 2 or the bi-direction TBU 100 of FIG. 1.
Changes in the NMOS threshold directly affect the trip current. For example, in the simulation shown in FIG. 3, the trip current is seen to vary widely when varying the threshold (Vth) of the NMOS over a range from −3.0V (the highest trip current in the simulation ˜200 mA) to −0.6V (˜40 mA) in 0.2V steps.
This indicates that for a given JFET resistance, the maximum allowable range of the NMOS threshold is from −3V to about −1.5V in this example. In practice, the allowable range of NMOS threshold-variation is less, because the JFET parameters also vary considerably. Results of a Monte Carlo analysis are show in FIG. 4, where the effect of the JFET parameters varying with a standard deviation of 5% and, simultaneously, the NMOS threshold-variation is from −1V to −3V. The Monte Carlo analysis assumes a Gaussian distribution of both parameters.
The resulting distribution of FIG. 4 shows the trip falls outside of the typical design targets of the 120-200 mA limits of this exemplary TBU by a considerable amount, with a mean value of 135 mA and a standard deviation of 27 mA (20%).
Accordingly, there is a need to develop a device to address the problem of the poorly controlled threshold voltage parameter in fabrication of a depletion mode transistor in a TBU.